This invention relates to a semiconductor integrated circuit (IC) device having a plurality of line selection signal lines (hereinafter referred to as word lines) and more particularly to such a semiconductor IC device which can prevent the voltage changes in a selected word line from affecting the adjacent non-selected word lines.
There are semiconductor IC devices in which many memory cells are arranged in a matrix formation within a chip such that one of these memory cells can be selected by means of an address signal for writing information on it or reading information from it. FIG. 2 shows a known word line selection circuit used in connection with a semiconductor IC circuit of this kind, having a large number of word lines W.sub.1, W.sub.2, . . . (only four word lines W.sub.1 -W.sub.4 shown for the purpose of explanation) disposed parallel with respect to one another and many memory cells connected to each of these word lines.
In order that a desired one of these word lines can be selected, each of the lines W.sub.1 -W.sub.4 has one end connected to one of MOS transistors T.sub.11 -T.sub.14 and also one of MOS transistors T.sub.21 -T.sub.24. The other terminals of the MOS transistors T.sub.11 -T.sub.14 are grounded, their gates being connected respectively to the NAND output of a line decoder P.sub.1 or P.sub.2 and the other terminals of the other MOS transistors T.sub.21 -T.sub.24 are connected to a set of word line driving circuits D.sub.1 and D.sub.2. The gates of the MOS transistors T.sub.21 -T.sub.24 are connected to the output terminals of the inverters I.sub.1 and I.sub.2 through MOS transistors which serve as loads. The outputs from the aforementioned NAND gates P.sub.1 and P.sub.2 are applied to the input terminals of these inverters I.sub.1 and I.sub.2.
With a group of word lines thus structured, pairs of mutually adjacent lines such as W.sub.1 and W.sub.2, or W.sub.3 and W.sub.4, may be considered to form a set. Within each of these sets, an output signal from a same NAND gate such as P.sub.1 or P.sub.2 is applied to the gates of MOS transistors T.sub.11 and T.sub.12 or T.sub.13 and T.sub.14 and an inverse output signal to the gates of MOS transistors T.sub.21 and T.sub.22 or T.sub.23 and T.sub.24 through the inverter I.sub.1 or I.sub.2. One of each set of word lines such as W.sub.1 and W.sub.3 is connected to a first word line driving circuit D.sub.1 and the other such as W.sub.2 and W.sub.4 to a second word line driving circuit D.sub.2.
Operation of the circuit described above is explained next for the situation where the word line W.sub.2 is selected.
In the beginning, the outputs from the NAND gates P.sub.1 and P.sub.2 are maintained at high levels, the outputs of the inverters I.sub.1 and I.sub.2 at low levels and the outputs of the word line driving circuits D.sub.1 and D.sub.2 also at low levels. When the word line W.sub.2 is selected, the output from the line decoder P.sub.1 connected to it changes to a low level and that of the inverter I.sub.1 therefore becomes high such that the MOS transistors T.sub.21 and T.sub.22 are switched on. Thereafter, a high-level selection signal is outputted from the second word line driving circuit D.sub.2 and this signal reaches the word line W.sub.2 through the MOS transistor T.sub.12. During this process, the word line W.sub.1, to which the output from the same MAND gate P.sub.1 is applied, is kept at a low level through the MOS transistor T.sub.21 by the first word line driving circuit D.sub.1 and the other word lines W.sub.3 and W.sub.4, to which the output from the NAND gate P.sub.2 is applied are kepy at low levels respectively through the MOST transistors T.sub.13 and T.sub.14. In summary, the voltage levels of the adjacent word lines W.sub.1, W.sub.3 and W.sub.4 do not rise due to capacitance between the lines (inter-line capacitance) even if the level of the word line W.sub.2 is raised when this line is selected.
When a circuit of the aforementioned type is actually designed, however, the separations between adjacent word lines are controlled by the size of the memory cells and other factors and it is difficult to arrange MOS transistors within a limited space and to connect wires to their gates in order to apply signals from NAND gates to them. Recently, extremely small memory cells are coming to be used, for example, in dynamic RAMs. In such devices, separations between word lines become accordingly smaller and it becomes a serious problem to arrange MOS transistors properly inside such a device.